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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16602
312-OUTPUT TFT-LCD FULL COLOR DRIVER
The PD16602 is a TFT-LCD source driver with full color display capability. It is ideal for 1024 x 768 pixel (XGA) class high definition displays. The internal circuit consists of 12 channels (4 x 3) of analog input pins, 12 channels of 16-bit shift registers and 312 channels of sample & hold circuits (2 latch type). Analog display signals are sampled in 12 channels simultaneously by the sample & hold circuits and they are output in the next line. The output voltage of the sample & hold circuits is as great as 10.5 VP-P and maintains high accuracy with an output deviation of 20 mVMAX. Inputting analog display signals that been -processed in the previous stage signal processing circuit allows realization of a high definition 256-gray-scale-equivalent full color display without requiring line inversion.
FEATURES
* 4 x 3 (RGB)-channel analog input allows display signal input wiring to be reduced. * High dynamic range (10.0 VP-PMIN. VDD2 = 11.0 V) * High accuracy sample & hold circuits (output deviation; 20 mVMAX., 5.0 mVTYP.) * High-speed sampling frequency (for both analog and digital; fmax. = 20 MHzMIN.) * Low power control (reduction of output buffer bias current) function on chip (operating power consumption; 82 mWTYP., VDD2 = 12.5 V) * Bi-directional data store function on chip * Corresponding to high-density mounting (slim TCP)
ORDERING INFORMATION
Part Number Package TCP
PD16602N- x x x
Document No. S10671EJ1V0DS00 (1st edition) Date Published August 1998 N CP(K) Printed in Japan
(c)
1998
PD16602
1. BLOCK DIAGRAM
R/L CLK
SPR S/D 1 2
SPL Bi-directional shift register (26 circuits) 26 VDD1 VSS1
1
2
Level shifter (26 circuits)
26
VDD2(D) VSS2(D)
DR0 to DR3 DG0 to DG3 DB0 to DB3 1 2
4 4 4 26
LPC PL/NL HS BIAS1 BIAS2 Sample & hold + output buffer circuit VDD2(A) VCOM VSS2(A) VSS2(C)
S1
S312
SAMPLE & HOLD + OUTPUT BUFFER CIRCUIT 1
BIAS1 - SW3 SW1 CH DR0 to DR3 DG0 to DG3 DB0 to DB3 - SW4 SW2 CH SPn PL/NL HS + BIAS2 (S/H)N (S/H)P Sn +
2
PD16602
SAMPLE & HOLD + OUTPUT BUFFER CIRCUIT 2
DR0 to DR3 DG0 to DG3 DB0 to DB3 HS PL/NL S/D
12 Sample and hold + Output buffer circuit
S1 S3 S5
PL/NL
S311
S2 Sample and hold + Output buffer circuit S4 S6
PL/NL
S312
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PD16602
2. PIN CONFIGURATION
VSS2(A) VSS2(A) VSS2(C) VSS2(C) VDD2(A) VDD2(A) VDD2(D) VDD2(D) VDD1 VDD1 SDB RLB CLK SPL BIAS1 DR0 DR1 DR2 DR3 DB0 DB1 DB2 DB3 DG0 DG1 DG2 DG3 BIAS2 VCOM SPR HSB PLNLB LPC TEST VSS1 VSS1 VSS2(D) VSS2(D) VDD2(A) VDD2(A) VSS2(C) VSS2(C) VSS2(A) VSS2(A)
S312 S311 S310 S309
(Copper Plated surface)
S4 S3 S2 S1
4
PD16602
3. PIN DESCRIPTION
Pin Symbol S1 to S312 CLK Pin Name Driver outputs Clock input Description Output pins for sampled analog image signals. When driven with VDD2 = 12.5 V, a 11.5 VP-P analog voltage whose input/output characteristic is gain 1 is output. This pin reads the start pulse at the rising of CLK and starts sampling of analog display signals in 12 channels simultaneously. The active edges of CLK are all rising edges. Analog image signal input pins. Please input analog display signals by inverting the polarity for each display line. The shift direction of the shift register is as follows. R/L = H (right shift) ; SPR input, S1 S312, SPL output R/L = L (left shift) ; SPL input, S312 S1, SPR output R/L = H (right shift) ; start pulse input pin R/L = L (left shift) ; start pulse output pin R/L = H (right shift) ; R/L = L (left shift) ; start pulse output pin start pulse input pin
DR0 to DR3 DG0 to DG3 DB0 to DB3 R/L
Analog display signal inputs Shift direction switching input Start pulse input/ output Start pulse input/ output Polarity inversion input
SPR SPL PL/NL
Note
S/D HS
Note
Arrangement switching input Horizontal synchronous input
LPC
Low power control input Bias voltage inputs Logic power supply Driver power supply Driver power supply Common power supply Logic ground Driver ground Driver ground Driver ground Test pin
BIAS1 BIAS2 VDD1 VDD2(D) VDD2(A) VCOM VSS1 VSS2(D) VSS2(A) VSS2(C) TEST
S/D = L; When PL/NL = H, Both odd number pin and even number pin samples negative analog display signals and outputs positive analog signals from the driver output. When PL/NL = L, Both odd number pin and even number pin samples positive analog display signals and outputs negative analog signals from the driver output. S/D = H; When PL/NL = H, Odd number pin samples negative analog display signals and outputs positive analog signals from the driver output. Even number pin samples positive analog display signals and outputs negative analog signals from the driver output. When PL/NL = L, Odd number pin samples positive analog display signals and outputs negative analog signals from the driver output. Even number pin samples negative analog display signals and outputs positive analog signals from the driver output. S/D = H; Complying with one side arrangement dot inverting. S/D = L; Complying with both sides arrangement dot inverting. This pin shuts off the output at the falling edge and then outputs analog display signals at the rising. When HS = L, after the driver output pin goes to high impedance this pin switches PL/NL and resets the internal hold capacity and output buffer to the VCOM level. This pin shuts off the output buffer low current supply and increases the output impedance. The LPC = "H" mode allows the static current consumption to be reduced by approximately 20 %. These pins control the current consumption of the output buffer by applying a stabilized external power supply. 3.3 V 0.3 V 13.5 VMAX. 13.5 VMAX. This pin applies the intermediate voltage of a stable LCD drive voltage from a voltage follower, etc. Logic ground High voltage block (level shifter) High voltage block (output buffer) High voltage block (sample & hold) "L" or left open
Note Sample & hold operation and reset operation of the output buffer capacitance and VCOM level are performed by the PL/NL and HS logic.
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PD16602
4. NOTES ON USE
(1) In order to prevent latch up breakdown, power should be applied in the order of: VDD1 logic input VDD2(D), (A) VBIAS1,2, VCOM analog display signal input, and turned off in the reverse order. This order should also be observed in transition periods. (2) VSS1, VSS2(D), VSS2(A) and VSS2(C) are connected in the diffusion layer, but also be sure to connect them externally. Do not share the sample & hold ground VSS2(C) with other ground wiring on the mount board, but connect it to the edge to the signal board. There is a possibility of high-voltage or logic type noise being superimposed onto the sample & hold circuit, damaging the analog characteristics (output deviation, etc.). (3) Likewise, to prevent the sample & hold characteristics from deteriorating, insert a bypass capacitor of 0.1 F between VDD1 and VSS1, and approximately 0.1 F between VDD2(D), sufficiently secured. evaluation. (4) When LPC = "H", stable current supply of the output buffer may be shut off, which will impede normal negative feedback, and when the LCD panel load is small, the output voltage may become abnormal. Normal operation is assured with approximately 10 k + 50 pF, but when the time constant is smaller than this, please set LPC = "L". (5) Data input/output relationship As shown below, irrespective of right shift and left shift.
Output Data S1 DR0 S2 DB0 S3 DG0 S4 DR1 S5 DB1 S6 DG1 S309 DG2 S310 DR3 S311 DB3 S312 DG3
(A)
and VSS2(D),
(A).
An unstable power
supply may cause a driver through current, preventing the output range of the output buffer from being Therefore, determine the capacitance of the bypass capacitor after a thorough
(6) Bias control method Externally applying a voltage to pins BIAS1 and BIAS2 can control the output buffer current consumption. In this case, the analog characteristics (output deviation, driving capability, response speed, etc.) will not change. Please refer to the configuration in the figure below for the actual circuit. Also refer to the same configuration for the VCOM voltage input circuit. Current per driver IC is as follws.
VDD2
100 AMIN. (per IC) 0.01 F
VBIAS1, VBIAS2, VCOM
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PD16602
5. FUNCTIONAL DESCRIPTION
(1) Input Specification of the analog display signal (n = 0 to 25, R/L = "H" or "L")
Display signal input terminal/Output terminal S/D PL/NL DR0 S12n + 1 H H L L H L (-) (+) (-) (+) DB0 S12n + 2 (+) (-) (-) (+) DG0 S12n + 3 (-) (+) (-) (+) DR1 S12n + 4 (+) (-) (-) (+) ----------DG2 S12n + 9 (-) (+) (-) (+) DR3 S12n + 10 (+) (-) (-) (+) DB3 S12n + 11 (-) (+) (-) (+) DG3 S12n + 12 (+) (-) (-) (+)
(+) : Please input the positive analog input signal. (-) : Please input the negative analog input signal. (2) Output Specification of the analog display signal * Single Bank Arrangement for dot inversion (S/D = "H") Polarity of the output voltage
Line No. 1 2 3 4 5 PL/NL H L H L H S1 (DR0) (+) (-) (+) (-) (+) S2 (DR0) (-) (+) (-) (+) (-) S3 (DG0) (+) (-) (+) (-) (+) S4 (DR1) (-) (+) (-) (+) (-) S5 (DB1) (+) (-) (+) (-) (+) S6 (DG1) (-) (+) (-) (+) (-) S7 (DR2) (+) (-) (+) (-) (+)
(+) : Positive analog output (Negative line sampling), (-) : Negative analog output (Positive line sampling) * Dual Bank Arrangement for dot inversion (S/D = "L") Polarity of the each output voltage
Input signal polarity Line No. PL/NL Upper side 1 2 3 4 H L H L Lower side L H L H S1 (DR0) (+) (-) (+) (-) (-) (+) (-) (+) Output Polarity of the upper driver IC's S2 (DB0) (+) (-) (+) (-) (-) (+) (-) (+) S3 (DG0) (+) (-) (+) (-) (-) (+) (-) (+) S4 (DR1) (+) (-) (+) (-) (-) (+) (-) (+)
767 768
H L
L H
(+) (-)
(-) (+) S312' (DG3')
(+) (-)
(-) (+) S311' (DB3')
(+) (-)
(-) (+) S310' (DR3')
(+) (-)
(-) (+) S309' (DG2')
Output polarity of the lower driver IC's
Sn : Output voltage of the upper side driver, Sn' : Output voltage of the lower side driver,
(+) : Positive output of the upper side driver (-) : Negative output of the lower side driver
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PD16602
(3) Sampling and hold timing (R/L = "L") S/D = "L" (Dual Bank Arrangement)
Line (N - 1) writing HS Line N writing Line (N + 1) writing
PL/NLNote
(S/H)P
Line (N - 1) output
Line (N + 1) sampling
Line (N + 1) output
(S/H)N
Line N sampling
Line N output
Line (N + 2) sampling
S1 to S312 Hi-Z
Positive output Line (N - 1) Hi-Z
Line N Negative output Hi-Z
Positive output Line (N + 1) Hi-Z
Note
PL/NL = H; input negative analog display signal. PL/NL = L; input positive analog display signal.
S/D = "H" (Single Bank Arrangement)
Line (N - 1) writing HS PL/NLNote Line N writing Line (N + 1) writing
(S/H)P of Add pin
Line (N - 1) output Line N sampling
Line (N + 1) sampling Line N output
Line (N + 1) output Line (N + 2) sampling
(S/H)N of Add pin
(S/H)P of Even pin
Line N sampling Line (N - 1) output
Line N output Line (N + 1) sampling
Line (N + 2) sampling Line (N + 1) output
(S/H)N of Even pin
S2n + 1 (Add pin)
Positive output Line (N - 1)
Line N Negative output
Positive output Line (N + 1)
S2n (Even pin) Hi-Z
Line (N - 1) Negative output Hi-Z
Positive output Line N Hi-Z
Line (N + 1) Negative output Hi-Z
Note
Odd number pin Even number pin
PL/NL = H; input negative analog display signal. PL/NL = L; input positive analog display signal. PL/NL = H; input positive analog display signal. PL/NL = L; input negative analog display signal.
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PD16602
(4) Relatonship with HS and PL/NL
HS tHS-SETUP PL/NL CLK 012 tHS-SP SPR (SPL) Hi-Z Output period 26 27 012 tHS-HOLD Sampling period
Caution HS and PL/NL edges have no relationship with clock timing.
Timing Item Horizontal synchronization setup time Horizontal synchronization hold time tHS-HOLD Symbol tHS-SETUP Description Setup time of PL/NL signal with respect to HS. Secure 50 nsMIN. at least. PL/NL hold time. Secure 250 nsMIN. at least. The hold capacitance at this time is at common potential VCOM, but the output buffer does not reach VCOM, and therefore sampling is not possible. Sampling start time tHS-SP Time for the output buffer to reach VCOM (reset level). Secure 1.0 sMIN at least. Sampling is possible at this time. Input the start pulse at this time.
These characteristics are specified by load constants of 50 k + 100 pF. (5) Internal sampling delay
CLK td1 SP1 td1 SP2 td2 td2
DR0 to DR3 (input)
DG0 to DG3 (input)
DB0 to DB3 (input)
Timing Duration CLK-sampling pulse delay
Symbol td1
Description Delay time between CLK signal and rising edge of internal sampling pulse SPn. Input an analog image signal with a timing difference of td1 in order to secure a sufficient sampling period.
Sampling pulse-CLK delay
td2
Delay time between CLK signal and falling edge of internal sampling pulse.
td1 is 22 5 ns and td2 is 14 5 ns (these are not guaranteed values).
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PD16602
(6) Cascade timing R/L = H (right shift)
0 CLK SPR SP1 SP2 SP26 1 2 26 1 2 3 4 5 24 25 26 27 28 29 30
SPL (Next stage SPR) SP1 SP2 27 28
DR0 to DR3 DG0 to DG3 DB0 to DB3
1
2
3
25
26
27
28
R/L = L (left shift)
0 CLK SPL SP26 SP25 SP1 1 2 26 1 2 3 4 5 24 25 26 27 28 29 30
SPL (Next stage SPL) SP26 SP25 27 28
DR0 to DR3 DG0 to DG3 DB0 to DB3
1
2
3
25
26
27
28
10
PD16602
6. ELECTRIC SPECIFICATION
ABSOLUTE MAXIMUM RATINGS (TA = 25C, VSS(D), (A), (C) = 0 V)
Item Logic supply voltage Logic input voltage Logic output voltage Driver supply voltage Display signal input voltage Driver output voltage Driver output current Operating temperature range Storage temperature range Symbol VDD1 VIN VO1 VDD2 (D), (A) VIN (A) VO2 IO2 TA Tstg Rating -0.5 to +6.5 -0.5 to VDD1 +0.5 -0.5 to VDD1 +0.5 -0.5 to +15 -0.5 to VDD2 +0.5 -0.5 to VDD2 +0.5 10 -10 to +75 -40 to +125 Unit V V V V V V mA C C
RECOMMENDED OPERATING RANGE (TA = -10 to 75C, VSS = 0 V)
Item Logic supply voltage High-level input voltage Low-level input voltage Driver supply voltage Display signal input Driver output voltage Bias current Bias voltage Symbol VDD1 VIH VIL VDD2 VIN (A) VO IBIAS1, 2 VBIAS1 VBIAS2 11.0 VSS +0.5 VSS +0.5 100 VSS +4.5 VDD2 -7.5 VSS +5.0 VDD2 -7.0 VSS +5.5 VDD2 -6.5 12.5 MIN. 3.0 0.7 VDD1 0.3 VDD1 13.5 VDD2 -0.5 VDD2 -0.5 TYP. 3.3 MAX. 3.6 Unit V V V V V V
A
V V
11
PD16602
+1.0 ELECTRICAL SPECIFICATIONS (TA = -10 to 75C, VDD1 = 3.3 V 0.3 V, VDD2 =12.5 V, VSS = 0 V) -1.5
Item High-level output voltage Low-level output voltage Input leakage current Driver output current (black level) Driver output current (white level) Driver output current (white level) Driver output current (black level) Output off leakage current Dynamic current consumption Symbol VOH VOL IiL IOH11 IOH12 IOH21 IOH22 IOFF IDD12 IDD22 Condition Logic, IOH1 = 0 mA Logic, IOL1 = 0 mA Vi = VDD1, VSS1 PL/NL = H (source) VO = 3.0 V PL/NL = L (sink) VO = 9.0 V VO2 = VDD2, VSS VDD1, fCLK = 20 MHz VDD2, fHS = 66 kHz, LPC = L, No load VDD2, fHS = 66 kHz, LPC = H, No load Static current consumption IDD21 VDD2, No load fHS = 66 kHz, LPC = L VDD2, No load fHS = 66 kHz, LPC = H Output deviation
Note
MIN. VDD1 -0.1
TYP.
MAX.
Unit V
0.1 10 VR = VG = VB = 11 V VR = VG = VB = 7 V VR = VG = VB = 5 V VR = VG = VB = 1 V 0.3 0.3 1 0.3 9.5 6.5 9.0 0.8 15 13 14 -0.3 -0.3
V
A
mA mA mA mA
A
mA mA mA mA
6.0 5.0 5.0
12 20 20
mA mV mV
VO
VR = VG = VB = 7 to 11 V, PL/NL = H VR = VG = VB = 1 to 5 V, PL/NL = L
Note The "deviation" indicates the minimum and maximum values in the driver output voltage distribution in the chip.
12
PD16602
SWITCHING CHARACTERISTICS (TA = -10 to +75C, VDD1 = 3.3 V 0.3 V, VDD2 =12.5
Item Start pulse output delay tIme Driver output delay time Symbol tPLH1 tPHL2 tPHL3 tPLH2 tPLH3 Input capacitance Ci1 Ci2 Ci3 Maximum clock frequency fmax. Logic except for SPR (SPL), TA = 25C SPR (SPL), TA = 25C Display signal input pin 20 CL = 20 pF CL = 50 pF, R = 50 k Condition MIN. 12
+1.0 V, VSS = 0 V) -1.5
TYP. 20 6.75 13.5 6.75 13.5 7 10 20 MAX. 40 11 17 11 17 10 15 Unit ns
s s s s
pF pF pF MHz
TIMING REQUIREMENT (TA = -10 to +75C, VDD1 = 3.3 V 0.3 V, VSS = 0 V, tr = tf = 5 ns)
Item Clock pulse width Horizontal synchronous signal pulse width Start pulse setup time CLK-sampling pulse delay time Sampling pulse-CLK delay time Horizontal synchronous signal setup time Horizontal synchronous signal hold time HS-start pulse time Start pulse-HS time Symbol PWCLK PWHS tSETUP td1 td2 tHS-SETUP tHS-HOLD tHS-SP tSP-HS 50 250 1.0 10 Condition Duty = 50 % MIN. 25 300 10 15 15 TYP. MAX. Unit ns ns ns ns ns ns ns
s
ns
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PD16602
SWITCHING CHARACTERISTICS (R/L = H) Unless otherwise specified, the input levels are all set to 0.5 VDD1
1/fmax. PWCLK PWCLK VDD1 90 % CLK tSETUP VDD1 SPR (SPL) tPLH VOH SPL (SPR) 10 % 10 % 90 % VSS1 tr tf
Items in ( ) apply when R/L = L.
VSS1
VOL VDD1
HS VSS1 PWHS tHS-SETUP tHS-HOLD VDD1 PL/NL VSS1 tHS-SP VDD1 SPR (input) VSS1 tSP-HS VDD1 SPR (input) VSS1
tPHL3 Hi-Z Sn VX tPLH3 VX Hi-Z Sm tPLH2 tPHL2 VDD2
VX refers to the final output voltage, tPLH2 and tPHL2 refer to the time required to an output precision level of 10 % (0.1 VX); and tPLH3 and tPHL3 refer to the time required to reach an output precision level of 6 bits.
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PD16602
RECOMMENDED MOUNTING CONDITIONS
When mounting this product, please make sure that the following recommended conditions are satisfied. For packaging methods and conditions other than those recommended below, please contact NEC sales personnel.
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350C, heating for 2 to 3 seconds; pressure 100 g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100C; pressure 3 to 8 kg/cm ; time 3 to 5 secs. 2 Real bonding 165 to 180C; pressure 25 to 45 kg/cm , time 30 to 40 secs. (When using the anisotropic conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.)
2
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. Reference NEC Semiconductor Device Reliability/Quality Control System (IEI-1212) Quality Grades on NEC Semiconductor Devices (C11531E)
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PD16602
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

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